Issue No. 01 - January (1986 vol. 35)
I. Koren , Department of Electrical Engineering, Technion?Israel Institute of Technology
The above paper<sup>1</sup>presents an approach to the design of fault- tolerant processor arrays. In Section IV of this paper (related work on fault-tolerant networks) the author criticizes a previously published approach presented by Koren  and by Gordon, Koren and Silberman . In , an algorithm for structuring a linear array on a rectangular grid of processing elements (PE's), some of w
I. Koren, "Comments on "The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors"," in IEEE Transactions on Computers, vol. 35, no. , pp. 93, 1986.