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In this paper, we propose a cost-effective design of circuit switching multistage interconnection networks (CSMIN's). Increase of the network bandwidth and reduction of the network size (and thus low costs) are both accomplished by network overlapping and memory interleaving (NOMI), instead of by increasing the number of switches or adding buffers. The NOMI and its control principle are described on the basis of the structure and interconnection functions of CSMIN's. Detailed accounts of both the network design and the drastic reduction in hardware costs are given. The impact of NOMI on system performance is also analyzed.
processor cluster, Asynchronous and synchronous multiplexing, bandwidth, blocking factor, circuit switching, memory cluster, multistage interconnection network, network overlapping and memory interleaving, pass rate
"A cost-effective multistage interconnection network with network overlapping and memory interleaving", IEEE Transactions on Computers, vol. 34, no. , pp. 1088-1101, Dec. 1985, doi:10.1109/TC.1985.6312208
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