The Community for Technology Leaders
Green Image
Issue No. 11 - November (1985 vol. 34)
ISSN: 0018-9340
pp: 1033-1044
J.A.B. Fortes , School of Electrical Engineering, Purdue University
A new approach to the design of gracefully degradable processor arrays is discussed. Fault tolerance and graceful degradation are achieved by simultaneously reconfiguring the processor array and the algorithm in execution. Two types of algorithm reconfigurability are considered, namely, row reconfigurability (RR) and row-column reconfigurability (RCR). correspondingly, two array reconfiguration schemes are discussed, i.e., successive row elimination (SRE) and alternate row-column elimination (ARCE). It is shown that the computations of any algorithm executable in a processor array can always be (re) organized so that the resultant algorithm has the RR and/or RCR properties. Upper bounds on the increase in execution time of an algorithm due to reorganization of computations for reconfigurability are derived. Detailed analysis of performance and reliability is done for both SRE and ARCE reconfiguration schemes. These reconfiguration techniques are applicable to any processor array and suitable for VLSI technology.
reliability, Algorithm transformations, computational availability, dynamic reconfiguration, graceful degradation, performability, processor arrays
C.S. Raghavendra, J.A.B. Fortes, "Gracefully Degradable Processor Arrays", IEEE Transactions on Computers, vol. 34, no. , pp. 1033-1044, November 1985, doi:10.1109/TC.1985.1676536
107 ms
(Ver 3.3 (11022016))