The Community for Technology Leaders
Green Image
Issue No. 10 - Oct. (1985 vol. 34)
ISSN: 0018-9340
pp: 968-972
Michel Dubois , Department of Electrical Engineering, University of Southern California, Los Angeles, CA 90089
Shared-memory multiprocessors to support concurrent languages for general-purpose multitasked systems are analyzed. To solve the traditional performance problems caused by memory access latency and conflicts, extensive caching of instructions and data is performed in each processor node. Caches are private to each processor, and coherence is maintained in hardware between the caches. To maintain a good efficiency, several contexts are resident in each processor. On a miss in the cache, a microswitch to another resident context is operated by changing the program counter and a pointer in the register memory. The instruction set of each processor is RISC-like, so that a microswitch should waste few machine cycles. The proposed system has high efficiency, even when the number of processors increases and when the coherence overhead and conflicts are high. Models are developed to evaluate throughput and efficiency.
throughput, Cache, efficiency, RISC architecture, shared-memory multiprocessor

M. Dubois, "A cache-based multiprocessor with high efficiency," in IEEE Transactions on Computers, vol. 34, no. , pp. 968-972, 1985.
89 ms
(Ver 3.3 (11022016))