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Memory interleaving and multiple access ports are the key to a high memory bandwidth in vector processor systems. Each of the active ports supports an independent access stream to memory among which access conflicts may arise. Such conflicts lead to a decrease in memory bandwidth. We present some analytical results for the calculation of the resulting effective bandwidth for one and two access streams to a memory system in a vector processor. In particular, conditions for conflict-free access are given together with some conflicting cases that should be avoided. Finally, examples of measurements on a Cray X-MP and corresponding simulations are presented.
memory access in vector mode, Barrier-situation, conflict-free access, interleaved memories, linked conflict
"On the effective bandwidth of interleaved memories in vector processor systems", IEEE Transactions on Computers, vol. 34, no. , pp. 949-957, Oct. 1985, doi:10.1109/TC.1985.6312199
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