Issue No. 10 - Oct. (1985 vol. 34)

ISSN: 0018-9340

pp: 892-901

Charles E. Leiserson , Laboratory for Computer Science, Massachusetts Institute of Technology, Cambridge, MA 02139

ABSTRACT

This paper presents a new class of universal routing networks called fat-trees, which might be used to interconnect the processors of a general-purpose parallel supercomputer. A fat-tree routing network is parameterized not only in the number of processors, but also in the amount of simultaneous communication it can support. Since communication can be scaled independently from number of processors, substantial hardware can be saved over, for example, hypercube-based networks, for such parallel processing applications as finite-element analysis, but without resorting to a special-purpose architecture. Of greater interest from a theoretical standpoint, however, is a proof that a fat-tree of a given size is nearly the best routing network of that size. This universality theorem is proved using a three-dimensional VLSI model that incorporates wiring as a direct cost. In this model, hardware size is measured as physical volume. We prove that for any given amount of communications hardware, a fat-tree built from that amount of hardware can simulate every other network built from the same amount of hardware, using only slightly more time (a polylogarithmic factor greater). The basic assumption we make of competing networks is the following. In unit time, at most O(a) bits can enter or leave a closed three-dimensional region with surface area a. (This paper proves the universality result for off-line simulations only.)

INDEX TERMS

VLSI theory, Fat-trees, interconnection networks, parallel supercomputing, routing networks, universality

CITATION

Charles E. Leiserson, "Fat-trees: Universal networks for hardware-efficient supercomputing",

*IEEE Transactions on Computers*, vol. 34, no. , pp. 892-901, Oct. 1985, doi:10.1109/TC.1985.6312192