Issue No. 08 - August (1985 vol. 34)

ISSN: 0018-9340

pp: 709-717

C.C. Wang , Communications Systems Research, Jet Propulsion Laboratory, California Institute of Technology

ABSTRACT

Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura [1] recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is also developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation.

INDEX TERMS

systolic array, Finite field inverse, finite field multiplication, finite field multiplier, inverse, Massey-Omura multiplier, normal basis, normal basis multiplier, pipeline

CITATION

J.K. Omura, I.S. Reed, C.C. Wang, H.M. Shao, T.K. Troung, L.J. Deutsch, "VLSI Architectures for Computing Multiplications and Inverses in GF(2<sup>m</sup>)",

*IEEE Transactions on Computers*, vol. 34, no. , pp. 709-717, August 1985, doi:10.1109/TC.1985.1676616SEARCH