Issue No. 03 - March (1985 vol. 34)
D.P. Agrawal , Department of Electrical and Computer Engineering, North Carolina State University
stuck-at faults, The emergence of multiple processor systems has seen the increased use of multistage interconnection networks (MIN's), built with several stages of 2-input 2-output switching elements (SE's). The connectivity and fault tolerance of these networks are important problems as MIN's are expected to be the heart of these systems. This paper employs a versatile graph model of an SE that could represent all possible stuck type terminal faults at the control lines and input/output data lines. This techni, Adjacency matrix, average distance, connectivity, dynamic full access capability, graph model, multistage interconnection networks, reachability matrix
D. Agrawal and n. Ja-Song Leu, "Dynamic Accessibility Testing and Path Length Optimization of Multistage Interconnection Networks," in IEEE Transactions on Computers, vol. 34, no. , pp. 255-266, 1985.