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Issue No. 02 - February (1985 vol. 34)
ISSN: 0018-9340
pp: 170-173
E.O. Nwachukwu , Department of Computer Science, University of Port Harcourt
This correspondence describes the implementation of a versatile hardware address indexing unit (AIU) capable of generating a multiplicity of address sequences for both array processing and array manipulation. The AIU utilizes a counter/multiplexer principle and incorporates an address logic for implementing real-value FFT based on a standard complex form.
real-value FFT, Address indexing unit, array processing and manipulation, counter/multiplexer principle

E. Nwachukwu, "Address Generation in an Array Processor," in IEEE Transactions on Computers, vol. 34, no. , pp. 170-173, 1985.
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