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Issue No. 08 - August (1984 vol. 33)
ISSN: 0018-9340
pp: 743-745
Javad Khakbaz , Center for Reliable Computing, Computer Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, CA 94305.; Memorex Corporatio
A new design of testable PLA's is presented. This design has the following characteristics: it requires little extra hardware; it has very little, if any, impact on the speed of the PLA in normal operation; it has very high fault coverage (all single and multiple stuck-at faults, crosspoint faults, and all combinations thereof are detected); and it can be used for designing testable folded PLA's. This design, however, is not appropriate for built-in test.

J. Khakbaz, "A Testable PLA Design with Low Overhead and High Fault Coverage," in IEEE Transactions on Computers, vol. 33, no. , pp. 743-745, 1984.
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