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Issue No. 08 - August (1984 vol. 33)
ISSN: 0018-9340
pp: 712-730
Butler W. Lampson , Xerox Palo Alto Research Center, Palo Alto, CA.; Systems Research Center, Digital Equipment Corporation, Palo Alto, CA.
Gene McDaniel , Xerox Palo Alto Research Center, Palo Alto, CA.; Western Research Laboratory, Digital Equipment Corporation, Los Altos, CA.
Severo M. Ornstein , Xerox Palo Alto Research Center, Palo Alto, CA.; Computer Professionals for Social Responsibility, Palo Alto, CA.
The instruction fetch unit (IFU) of the Dorado personal computer speeds up the emulation of instructions by prefetching, decoding, and preparing later instructions in parallel with the execution of earlier ones. It dispatches the machine's microcoded processor to the proper starting address for each instruction, and passes the instruction's fields to the processor on demand. A writeable decoding memory allows the IFU to be specialized to a particular instruction set, as long as the instructions are an integral number of bytes long. There are implementations of specialized instruction sets for the Mesa, Lisp, and Smalltalk languages. The IFU is implemented with a six-stage pipeline, and can decode an instruction every 60 ns. Under favorable conditions the Dorado can execute instructions at this peak rate (16 mips).

G. McDaniel, S. M. Ornstein and B. W. Lampson, "An Instruction Fetch Unit for a High-Performance Personal Computer," in IEEE Transactions on Computers, vol. 33, no. , pp. 712-730, 1984.
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