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Issue No. 06 - June (1984 vol. 33)
ISSN: 0018-9340
pp: 493-506
Y. Tamir , Computer Science Division, Department of Electrical Engineering and Computer Sciences, University of California
A high probability of detecting errors caused by hardware faults is an essential property of any fault-tolerant system. VLSI technology makes the use of duplication and matching for error detection practical and attractive. A critical circuit in this context is a self-testing comparator. Faults in the comparator must be detected so that they do not mask discrepancies between the duplicated modules.
two-rail code checker, Concurrent error detection, duplication and matching, faults in VLSI circuits, MOS PLA fault model, programmable logic array, self-testing comparator
C.H. Sequin, Y. Tamir, "Design and Application of Self-Testing Comparators Implemented with MOS PLA's", IEEE Transactions on Computers, vol. 33, no. , pp. 493-506, June 1984, doi:10.1109/TC.1984.1676473
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