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Issue No. 05 - May (1984 vol. 33)
ISSN: 0018-9340
pp: 414-426
E.H. Wold , Computer Sciences Division, University of California
In some signal processing applications, it is desirable to build very high performance fast Fourier transform (FFT) processors. To meet the performance requirements, these processors are typically highly pipelined. Until the advent of VLSI, it was not possible to build a single chip which could be used to construct pipeline FFT processors of a reasonable size. However, VLSI implementations have constraints which differ from those of discrete implementations, requiring another look at some of the typical FFT'algorithms in the light of these constraints.
signal processing, CORDIC, fast Fourier transform, integrated circuits, parallel processors, pipeline processors
E.H. Wold, A.M. Despain, "Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations", IEEE Transactions on Computers, vol. 33, no. , pp. 414-426, May 1984, doi:10.1109/TC.1984.1676458
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