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Issue No. 12 - December (vol. 32)
ISSN: 0018-9340

IEEE Computer Society (PDF)

pp. c2

An Inductive Assertion Method for Register Transfer Level Design Verification (Abstract)

V. Pitchumani , Department of Electrical and Computer Engineering, Syracuse University
pp. 1073-1080

Design and Performance of Generalized Interconnection Networks (PDF)

L.N. Bhuyan , Department of Electrical and Computer Engineering, University of Southwestern Louisiana
pp. 1081-1090

The Performance of Multistage Interconnection Networks for Multiprocessors (Abstract)

C.P. Kruskal , Department of Computer Science, University of Illinois
pp. 1091-1098

A Class of Redundant Path Multistage Interconnection Networks (PDF)

K. Padmanabhan , Laboratory for Advanced Supercomputers, Department of Computer Science, University of Illinois
pp. 1099-1108

Optimal Parallel Scheduling of Gaussian Elimination DAG's (Abstract)

M.A. Srinivas , Department of Computer Science, Pennsylvania State University
pp. 1109-1117

Ultrahigh Reliability Prediction for Fault-Tolerant Computer Systems (Abstract)

R.M. Geist , Department of Computer Science, Duke University
pp. 1118-1127

A Pipelined Distributed Arithmetic PFFT Processor (Abstract)

P. Chow , Department of Electrical Engineering, University of Toronto
pp. 1128-1136

On the Acceleration of Test Generation Algorithms (PDF)

H. Fujiwara , Department of Electronic Engineering, Osaka University
pp. 1137-1144

Exhaustive Test Pattern Generation with Constant Weight Vectors (Abstract)

D.T. Tang , IBM Thomas J. Watson Research Center
pp. 1145-1150

Two-Level Replacement Decisions in Paging Stores (Abstract)

O. Babaoglu , Department of Computer Science, Cornell University
pp. 1151-1159

VLSI Array Design Under Constraint of Limited I/O Bandwidth (Abstract)

P.S. Liu , Department of Electrical and Computer Engineering, University of Miami
pp. 1160-1170

The VLSI Complexity of Sorting (Abstract)

C.D. Thompson , Computer Science Division, University of California
pp. 1171-1184

Transposition of Matrix Stored on Sequential File (Abstract)

D.W. Twigg , Boeing Computer Services Company
pp. 1185-1188

A Preliminary Evaluation of Trace Scheduling for Global Microcode Compaction (Abstract)

R. Grishman , Department of Computer Science, New York University
pp. 1191-1194

Universal Tests for Detection of Input/Output Stuck-At and Bridging Faults (Abstract)

M. Karpovksy , Department of Computer Science, School of Advanced Technology, State University of New York
pp. 1194-1198

Good Controllability and Observability Do Not Guarantee Good Testability (Abstract)

J. Savir , IBM Thomas J. Watson Research Center
pp. 1198-1200

Comments on "Optimal Design of Distributed Information Systems" (PDF)

C.E. Veni Madhavan , National Informatics Centre, Electronics Commission
pp. 1200-1201

Optimal Algorithms for the Intersection and the Minimum Distance Problems Between Planar Polygons (Abstract)

F. Chin , Department of Computer Science, Chinese University of Hong Kong
pp. 1203-1207

Measured Flip-Flop Responses to Marginal Triggering (Abstract)

T.J. Chaney , Computer Systems Laboratory, Washington University
pp. 1207-1209

A Faster 8-Bit Carry Circuit (Abstract)

R. Kallman , Department of Mathematical Sciences, Ball State University
pp. 1209-1211

Symmetric and Threshold Boolean Functions Are Exhaustive (Abstract)

B.M.E. Moret , Department of Computer Science, University of New Mexico
pp. 1211-1212

Information for Authors (PDF)

pp. 1212
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