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Issue No. 08 - August (1983 vol. 32)
ISSN: 0018-9340
pp: 745-747
N. Bandeira , Department of Electrical and Computer Engineering, University of California
A new algorithm for implementing the two's complement multiplication of an m ? n bit number is described. By interpreting certain positive partial product bits as negative, a parallel array is developed which has the advantage of using only one type of adder cell. A comparison with the Pezaris and Baugh-Wooley arrays is presented, showing that the new array is as fast as the Pezaris array and uses less hardware than the Baugh-Wooley implementation.
Pezaris multiplier, Array multiplier, Baugh-Wooley multiplier, binary multiplication, celluar-subtractor multiplier, parallel multiplier
K. Vaccaro, J.A. Howard, N. Bandeira, "A Two's Complement Array Multiplier Using True Values of the Operands", IEEE Transactions on Computers, vol. 32, no. , pp. 745-747, August 1983, doi:10.1109/TC.1983.1676312
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