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Issue No. 05 - May (1983 vol. 32)
ISSN: 0018-9340
pp: 501-504
F.J. Taylor , Department of Electrical and Computer Engineering, University of Cincinnati
Residue arithmetic is receiving increased attention due to its ability to support very high-speed parallel arithmetic. However, dynamic range overflow remains a serious problem. Contemporary overflow management schemes rely on inefficient scaling algorithms. In this paper, an overflow-inhibiting residue multiplier is architected and tested. The system makes use the popularthree moduliset{2n - 1,2n, 2"+ 1}. Based on 4K high-speed memory technology, a practical 16-bit multiplier can be configured. An error model for the derived residue arithmetic unit is presented and experimentally verified.
residue numbers, Dynamic range overflow, error model, fixed-point multiplier

F. Taylor, "An Overflow-Free Residue Multiplier," in IEEE Transactions on Computers, vol. 32, no. , pp. 501-504, 1983.
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