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Issue No. 05 - May (1983 vol. 32)
ISSN: 0018-9340
pp: 425-438
J.E. Requa , Lawrence Livermore National Laboratory
This paper presents the design and a brief analysis of the Piecewise Data Flow computer (PDF), an architecture proposed for very high-performance computing. PDF is a heterogeneous multiprocessor system having both SIMD and MIMD characteristics. Each computation is translated into a control flow graph in which each node contains a basic block of instructions. Concurrency can be exploited in three different ways: simultaneous execution of independent basic blocks, simultaneous execution of independent instructions within a basic block, and intrinsic array operations. This program representation is amenable to traditional languages (e.g., Fortran) because almost all optimizing compilers use basic blocks as their internal representation. New functional languages should be able to exploit this architecture even more easily. The most significant aspects of the PDF architecture concern scheduling basic blocks for execution, allocating registers to intermediate results, and assigning instructions to processors.
supercomputer architecture, Array processors, concurrent execution, data flow machine, multiprocessors, program representation
J.E. Requa, J.R. McGraw, "The Piecewise Data Flow Architecture: Architectural Concepts", IEEE Transactions on Computers, vol. 32, no. , pp. 425-438, May 1983, doi:10.1109/TC.1983.1676253
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