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Issue No. 04 - April (1983 vol. 32)
ISSN: 0018-9340
pp: 402-406
M.J. Irwin , Department of Computer Science, Pennsylvania State University
Research in computer architecture in the last decade has been driven largely by the motivation to overcome the "von Neumann" bottleneck. This paper describes the design and use of one such architecture?fully digit on-line networks. First, digit on-line algorithms and processing are defined. The key advantage to digit on-line processing is that it allows a digit serial, most significant digit first, type of data flow. Processing of the most significant operand digits starts immediately and generation of the most significant result digits soon follows. The minimum set of primitive logic operations required to implement a digit on-line processing component in VLSI are outlined. Then, digit on-line networks consisting of many of these digit on-line components are examined. Finally, two different network configurations are discussed and compared.
systolic arrays, Digit on-line algorithms, digit on-line architectures, linear recurrences, pipelining, redundant digit sets

M. Irwin and R. Owens, "Fully Digit On-Line Networks," in IEEE Transactions on Computers, vol. 32, no. , pp. 402-406, 1983.
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