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Issue No. 04 - April (1983 vol. 32)
ISSN: 0018-9340
pp: 388-396
W.K. Jenkins , Department of Electrical Engineering and the Coordinated Science Laboratory, University of Illinois
During the last few years residue number (RNS) arithmetic has gained increasing importance for providing high speed fault tolerant performance in dedicated digital signal processors. One factor that has limited the use of redundant RNS theory in practice is the hardware complexity of the error checker. This paper presents a mathematical analysis of the error correction algorithm which suggests a new design with considerably reduced hardware complexity. A hardward architecture for a high speed pipelined error checker is proposed.
special purpose hardware, Digital processors, fault tolerance, modular arithmetic, residue arithmetic, self-checking arithmetic
W.K. Jenkins, "The Design of Error Checkers for Self-Checking Residue Number Arithmetic", IEEE Transactions on Computers, vol. 32, no. , pp. 388-396, April 1983, doi:10.1109/TC.1983.1676240
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