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Issue No. 01 - January (1983 vol. 32)
ISSN: 0018-9340
pp: 48-59
F.A. Briggs , Department of Electrical Engineering, Rice University
ABSTRACT
A possible design alternative for improving the performance of a multiprocessor system is to insert a private cache between each processor and the shared memory. The caches act as high-speed buffers by reducing the effective memory access time, and affect the delays caused by memory conflicts. In this paper, we study the effectiveness of caches in a multiprocessor system. The shared memory is pipelined and interleaved to improve the block transfer rate, and it assumes a two-dimensional organization, previously studied under random and word access. An approximate model is developed to estimate the processor utilization and the speed-up improvement provided by the caches.
INDEX TERMS
performance evaluation, Cache memories, memory organization, multicache consistency, multiprocessors
CITATION

M. Dubois and F. Briggs, "Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories," in IEEE Transactions on Computers, vol. 32, no. , pp. 48-59, 1983.
doi:10.1109/TC.1983.1676123
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