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Issue No. 10 - October (1982 vol. 31)
ISSN: 0018-9340
pp: 969-983
F.A. Briggs , Department of Electrical Engineering, Rice University
The PUMPS architecture consists of P task processing units (TPU) which share a pool of special peripheral processors, VLSI functional units, and a common two-dimensional shared memory (SM) via a block transfer oriented interconnection network. A shared cache is provided between the TPU's and SM for efficient MIMD interprocessor communication. The SM is also connected via a backend database management network (BDMN) with distributed control to the file memories, which are disk-based database storage devices.
VLSI computing structures, Image database management, multiprocessor architecture, pattern analysis, reconfigurable, architecture, resource sharing
null Kai Hwang, null King-Sun Fu, F.A. Briggs, B.W. Wah, "PUMPS Architecture for Pattern Analysis and Image Database Management", IEEE Transactions on Computers, vol. 31, no. , pp. 969-983, October 1982, doi:10.1109/TC.1982.1675906
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