Issue No.06 - June (1982 vol.31)
H. Fujiwara , Department of Electronic Engineering, Osaka University
In this correspondence we analyze the computational complexity of fault detection problems for combinational circuits and propose an approach to design for testability. Although major fault detection problems have been known to be in general NP-complete, they were proven for rather complex circuits. In this correspondence we show that these are still NP-complete even for monotone circuits, and thus for unate circuits. We show that for k-level (k = 3) monotone/unate circuits these problems are still NP-complete, but that these are solvable in polynomial time for 2-level monotone/unate circuits. A class of circuits for which these fault detection problems are solvable in polynomial time is presented. Ripple-carry adders, decoder circuits, linear circuits, etc., belong to this class. A design approach is also presented in which an arbitrary given circuit is changed to such an easily testable circuit by inserting a few additional test-points.
test generation, Combinational circuits, computational complexity, design for testability, fault detection, polynomial algorithms
H. Fujiwara, S. Toida, "The Complexity of Fault Detection Problems for Combinational Logic Circuits", IEEE Transactions on Computers, vol.31, no. 6, pp. 555-560, June 1982, doi:10.1109/TC.1982.1676041