IEEE Transactions on Computers - Table of contents (PDF)

IEEE Computer Society (PDF)

A DAG-Based Algorithm for Prevention of Store-and-Forward Deadlock in Packet Networks (PDF)

The Memory System of a High-Performance Personal Computer (Abstract)

Congestion Control of Packet Communication Networks by Input Buffer Limits?A Simulation Study (Abstract)

Fault-Diagnosis for a Class of Multistage Interconnection Networks (Abstract)

Error Complexity Analysis of Algorithms for Matrix Multiplication and Matrix Chain Product (Abstract)

Performance of Processor-Memory Interconnections for Multiprocessors (Abstract)

On the Buffer Behavior with Poisson Arrivals, Priority Service, and Random Server Interruptions (Abstract)

An Optimal Algorithm for Scheduling Requests on Interleaved Memories for a Pipelined Processor (Abstract)

A Hard Programmable Control Unit Design Using VLSI Technology (PDF)

An Improvement of Reliability of Memory System with Skewing Reconfiguration (Abstract)

Comments on "Concurrent Search and Insertion in AVL Trees" (PDF)

Correction to "Complete Solution of Boolean Equations" (PDF)

The Degradation in Memory Utilization Due to Dependencies (PDF)

Correction to "The Mpg System: A Machine-Independent Efficient Microprogram Generator" (PDF)

Correction to "Dual-Mode Logic for Function-Independent Fault Testing" (PDF)

Correction to "An Efficient Method for Improving Reliability of a Pipeline FFT" (PDF)

Planned Special Issues IEEE Transactions on Computers (PDF)

IEEE Computer Society Publications (PDF)

Call for Papers Trends and Applications (PDF)