Issue No. 08 - August (1981 vol. 30)
J.R. VanAken , MOS Microcomputer Department
A nem multiple-processor architecture is described that can exploit the instruction level concurrency in numerical processing tasks. The expression processor contains multiple processing elements (PE's), which can be configured either as an SIMD  array or as an expression tree pipeline. An expression tree is the parse tree conctructed by a compiler from an arithmetic or logical expression. The expression tree pipeline, or "X-Pipe," is a binary-tree networks of PE'S upon which expression tress are executed intact.A series of expression trees can be executed in pipelined fashion for enhanced concurrency. With this capability, the expression processor can exploit the concurrency in vector merges and scalar tasks, as well as conventional vector tasks. The architecture is designed for low-cost implementation using large-scale in (LSI) components.
parallelism, Arithmetic expression, binary-tree network, multiple-processor architecture, overlap and pipelining
G.L. Zick, J.R. VanAken, "The Expression Processor: A Pipelined, Multiple- Processor Architecture", IEEE Transactions on Computers, vol. 30, no. , pp. 525-536, August 1981, doi:10.1109/TC.1981.1675837