Issue No. 03 - March (1981 vol. 30)
A. Sengupta , Computer Science Unit, Indian Statistical Institute
This correspondence deals with the fault-tolerant realization of a sequential machine using error-correcting (n,k) linear codes. Earlier works in the same area confine their attention to modified Reed-Muller Code and perfect Hamming Code and achieve the realization using a number of majority logic gates, which makes the entire realization quite complex. The realization discussed in this paper needs a smaller number of circuit components with less complexity.
linear code, Correction, fault detection, fault masking, fault-tolerant machine
A. Sengupta, A. Palit, A. Bandyopadhyay, D. Chattopadhyay and A. Choudhury, "Realization of Fault-Tolerant Machines?Linear Code Application," in IEEE Transactions on Computers, vol. 30, no. , pp. 237-240, 1981.