Issue No. 10 - October (1980 vol. 29)
L. Dadda , Istituto di Elettrotecnica ed Elettronica Politecnico di Milano
A graphical representation is presented for parallel counters, i.e., multiple input combinatorial modules that count the number of inputs being in a given state (normally logic ONE).
response counters, Associative processors, carry-shower counters, digital counters, multiple input adders, parallel counter networks, parallel counters, parallel multipliers
L. Dadda, "Composite Parallel Counters," in IEEE Transactions on Computers, vol. 29, no. , pp. 942-946, 1980.