The Community for Technology Leaders
Green Image
Issue No. 06 - June (1980 vol. 29)
ISSN: 0018-9340
pp: 442-451
J. Savir , IBM Thomas J. Watson Research Center
ABSTRACT
Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size.
INDEX TERMS
stuck-at fault, Combinational circuit, fan-out-free circuit, minterm, prime implicant, single fault
CITATION
J. Savir, "Syndrome-Testable Design of Combinational Circuits", IEEE Transactions on Computers, vol. 29, no. , pp. 442-451, June 1980, doi:10.1109/TC.1980.1675603
92 ms
(Ver 3.3 (11022016))