Issue No. 12 - December (1979 vol. 28)
J.V. Blankenbaker , International Communication Sciences
The results for different hardware configurations of inner product computers presented by Swartzlander et al.1 are in error. In their Table I, the pipelined quasi-serial processor is credited with the ability to evaluate a complete inner product in 10 ns. The clock rate may be 10 ns but several clocks are required to evaluate one inner product. (Note the serial adder feeding the result register in their Fig. 2.)
J. Blankenbaker, "Comments on "Inner Product Computers"," in IEEE Transactions on Computers, vol. 28, no. , pp. 944, 1979.