Issue No. 09 - September (1979 vol. 28)

ISSN: 0018-9340

pp: 609-617

Y. Kambayashi , School of Computer Science, McGill University

ABSTRACT

Compared with random logic circuits, memory-type circuits are more suitable for LSI realization since their iterated structure of identical cells results in higher transistor density and higher yield. A programmable logic array (PLA) is a read only memory (ROM) with programmable addresses and it is suitable for realizing logic functions with many unspecified input combinations. For such a function, reduction of the number of input is possible in many cases. Since the cost of a PLA is mainly determined by the number of pins and the chip, both of which are affected by the number of inputs, the reduction of the number of inputs is very important in PLA design. On the other hand, the reduction of the number of product terms in a sum-of-product expression is important in conventional random logic synthesis. Since there is a tradeoff problem between the number of inputs and the number of product terms, we give a design procedure by the following preference order: 1) minimizing the number of pins, 2) minimizing the number of product terms, 3) minimizing the number of circuits used in the PLA. These factors also determine the area required for a chip.

INDEX TERMS

two-level circuit, Incompletely specified logic function, logic design, multiple-output function, programmable logic array, reduction of the number of inputs

CITATION

Y. Kambayashi, "Logic Design of Programmable Logic Arrays",

*IEEE Transactions on Computers*, vol. 28, no. , pp. 609-617, September 1979, doi:10.1109/TC.1979.1675428