Issue No. 09 - September (1976 vol. 25)

ISSN: 0018-9340

pp: 893-907

S. Muroga , Department of Computer Science, University of Illinois

ABSTRACT

Based on the intuitive observation that smaller numbers of gates and connections would usually lead to a more compact network on an integrated circuit (IC), a monotonically increasing function of gate count and connection count is concluded to be a reasonable cost function to be minimized in the logical design of a network implemented in IC. Then it is shown that all minimal solutions of such a cost function always can be found among the following: minimal networks with a minimal number of gates as the first objective and a minimal number of connections as the second objective; minimal networks with a minimal number of connections as the first objective and a minimal number of gates as the second objective; and minimal networks which are associated with the above two types of minimal networks. All three of these types of minimal networks of NOR gates, as an example, are calculated by logical design programs based on integer programming, for all functions of 3 or less variables and also some functions of 4 variables which require 5 or less NOR gates. According to the computational results, for the majority of the functions the first type of minimal networks is identical to the second type, and for no function were networks of the third type found to exist.

INDEX TERMS

Branch-and-bound method, emitter-coupled logic (ECL), generalized cost function, implicit enumeration method, integer programming, integrated circuit, integrated injection logic (IIL), logical design, minimization of the number of connections, minimization of the number of gates, NAND gates, NOR gates.

CITATION

S. Muroga and n. Hung Chi Lai, "Minimization of Logic Networks Under a Generalized Cost Function," in

*IEEE Transactions on Computers*, vol. 25, no. , pp. 893-907, 1976.

doi:10.1109/TC.1976.1674714

CITATIONS