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TABLE OF CONTENTS
Issue No. 06 - June (vol. 25)
ISSN: 0018-9340
Papers

IEEE Computer Society (PDF)

pp. c2

Implementation of an Experimental Fault-Tolerant Memory System (Abstract)

W.C. Carter , IBM Thomas J. Watson Research Center
pp. 557-568

A Highly Efficient Redundancy Scheme: Self-Purging Redundancy (Abstract)

J. Losq , Digital Systems Laboratory, Department of Electrical Engineering and Department of Computer Science, Stanford University
pp. 569-578

Computation-Based Reliability Analysis (Abstract)

J.F. Meyer , Department of Electrical and Computer Engineering (Program in Computer, Information, and Control Engineering) and the Department of Computer and Communication Sciences, University of Michigan
pp. 578-584

A Theory of Diagnosability of Digital Systems (Abstract)

F. Barsi , Istituto di Elaborazione dell'Informazione del C.N.R.
pp. 585-593

Truth-Table Verification of an Iterative Logic Array (Abstract)

F.J.O. Dias , Department of Electrical Engineering, Escola Polit?cnica, University of S?o Paulo
pp. 605-613

Transition Count Testing of Combinational Logic Circuits (Abstract)

J.P. Hayes , Department of Electrical Engineering and the Computer Science Program, University of Southern California
pp. 613-620

A Logic System for Fault Test Generation (Abstract)

S.B., Jr. Akers , Electronics Laboratory, General Electric Company
pp. 620-630

A Nine-Valued Circuit Model for Test Generation (Abstract)

P. Muth , Brown, Boveri, and Cie AG
pp. 630-636

Fail-Safe Asynchronous Machines with Multiple-Input Changes (Abstract)

H.Y.H. Chuang , Department of Computer Science, University of Pittsburgh
pp. 637-642

A Double Track Error-Correction Code for Magnetic Tape (Abstract)

P. Prusinkiewicz , Department of Computer Science, Faculty of Electronics, Warsaw Technical University
pp. 642-645

Processor Testability and Design Consequences (Abstract)

C. Robach , ENSIMAG, University of Grenoble
pp. 645-652

Recursion and Testing of Combinational Circuits (Abstract)

C. Turcat , ENSIMAG, University of Grenoble
pp. 652-654

The Error Latency of a Fault in a Sequential Digital Circuit (Abstract)

J.J. Shedletsky , Digital Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University
pp. 655-659

About Random Fault Detection of Combinational Networks (Abstract)

R. David , Laboratoire d'Automatique de Grenoble
pp. 659-664

On Monte Carlo Testing of Logic Tree Networks (Abstract)

P. Agrawal , Department of Electrical Engineering, University of Southern California
pp. 664-667

1975 List of Reviewers (PDF)

pp. 668-672
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