Issue No. 06 - June (1976 vol. 25)
J.J. Shedletsky , Digital Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University
In digital circuits there is typically a delay between the occurrence of a fault and the first error in the output. This delay is the error latency of the fault. A model to characterize the error latency of a fault in a sequential circuit is presented.
Error latency, input probability, latency interval, Markov chain, random testing, sequential circuits.
E.J. McCluskey, J.J. Shedletsky, "The Error Latency of a Fault in a Sequential Digital Circuit", IEEE Transactions on Computers, vol. 25, no. , pp. 655-659, June 1976, doi:10.1109/TC.1976.1674668