Issue No. 03 - March (1975 vol. 24)

ISSN: 0018-9340

pp: 233-242

S.S. Yau , Department of Computer Sciences and Electrical Engineering and the Biomedical Engineering Center, Northwestern University

ABSTRACT

An algorithm for generating test sets to detect all the multiple stuck-at-faults in combinational logic circuits is presented. This algorithm generates a test set using a set of functions, called representative functions, which consists of much fewer functions than all possible multiple stuck-at fault functions, but is sufficient for test generation. Two different methods of finding such a set of representative functions are presented. The test sets derived from the set of representative functions obtained by the first method will be smaller than that by the second method, but the second method is much simpler than the first especially for highly redundant circuits. Nevertheless, the complexity of this algorithm using the first method is about the same as that of Bossen and Hong's algorithm which is the simplest existing algorithm under the multiple stuck-at fault assumption, and yet the number of tests in a test set generated will always be smaller for redundant circuits and the same for irredundant circuits as that generated by Bossen and Hong's algorithm for irredundant circuits.

INDEX TERMS

Algorithms, combinational logic circuits, fault detections, fault functions, multiple stuck-at faults, redundant circuits, representative sets.

CITATION

null Shih-Chien Yang, S.S. Yau, "Multiple Fault Detection for Combinational Logic Circuits",

*IEEE Transactions on Computers*, vol. 24, no. , pp. 233-242, March 1975, doi:10.1109/T-C.1975.224204