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ABSTRACT
A comparison of the central processing unit (CPU) time and storage requirements for the parallel and deductive fault simulation techniques is presented. Versions of a parallel and deductive simulator were implemented and the comparison performed on an IBM System/360 Model 67 by simulating representative circuits including shift registers, sequencers, counters, two memory units, and a processor. Th
INDEX TERMS
Deductive simulation method, fault diagnosis, fault simulation, logic design verification, parallel simulation method.
CITATION

C. Elmendorf, S. Chappell, L. Schmidt and H. Chang, "Comparison of Parallel and Deductive Fault Simulation Methods," in IEEE Transactions on Computers, vol. 23, no. , pp. 1132-1138, 1974.
doi:10.1109/T-C.1974.223820
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