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Issue No.02 - February (1974 vol.23)
pp: 186-188
D.H. Sawin , Naval Electronics Laboratory Center
Tan recently developed a heuristic state assignment algorithm for asynchronous sequential circuits. This note extends Tan's procedure to include optimization of the output state logic, as well as the next state logic, and single-output-change (SOC) flow tables with DON'T CARE entries. The extended algorithm exhibits the same simplicity of execution as Tan's procedure.
Asynchronous sequential machines, internal state assignments, logic circuit realizations, single-transition-time (STT) sequential circuit realizations.
D.H. Sawin, "Optimization of Asynchronous Sequential Circuit Realizations", IEEE Transactions on Computers, vol.23, no. 2, pp. 186-188, February 1974, doi:10.1109/T-C.1974.223884
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