Issue No. 02 - February (1974 vol. 23)
D.H. Sawin , Naval Electronics Laboratory Center
Tan recently developed a heuristic state assignment algorithm for asynchronous sequential circuits. This note extends Tan's procedure to include optimization of the output state logic, as well as the next state logic, and single-output-change (SOC) flow tables with DON'T CARE entries. The extended algorithm exhibits the same simplicity of execution as Tan's procedure.
Asynchronous sequential machines, internal state assignments, logic circuit realizations, single-transition-time (STT) sequential circuit realizations.
D. Sawin, "Optimization of Asynchronous Sequential Circuit Realizations," in IEEE Transactions on Computers, vol. 23, no. , pp. 186-188, 1974.