ABSTRACT

An algorithm for high-speed, two's complement, m-bit by n-bit parallel array multiplication is described. The two's complement multiplication is converted to an equivalent parallel array addition problem in which each partial product bit is the AND of a multiplier bit and a multiplicand bit, and the signs of all the partial product bits are positive.

INDEX TERMS

Array multiplier, binary multiplication, high-performance multiplication, parallel multiplier, two's complement multiplication.

CITATION

C. Baugh and B. Wooley, "A Two's Complement Parallel Array Multiplication Algorithm," in

*IEEE Transactions on Computers*, vol. 22, no. , pp. 1045-1047, 1973.

doi:10.1109/T-C.1973.223648

CITATIONS