Issue No.04 - April (1973 vol.22)
E.E. Swartzlander , Hughes Aircraft Company
A novel technique for digital multiplication is presented that represents a considerable departure from conventional (i.e., add and shift or fully parallel) multiplication algorithms. The quasi-serial multiplier generates the bits of the product sequentially from least significant to most significant. Each bit is computed by "counting" the number of ones in the corresponding column of the bit-product matrix and adding the previous carrys. This single operation yields both the product bit and the carrys for the next column. The quasi-serial multiplier requires 2n of these count and add operations to determine the product of two n-bit numbers.
Current summing counters, digital multipliers, fast multipliers, full-adder counters, multiplier speed-simplicity comparison, parallel counters, quasi-serial multiplier.
E.E. Swartzlander, "The Quasi-Serial Multiplier", IEEE Transactions on Computers, vol.22, no. 4, pp. 317-321, April 1973, doi:10.1109/T-C.1973.223717