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Issue No. 12 - December (1972 vol. 21)
ISSN: 0018-9340
pp: 1426-1430
R.C. Dorr , Bell Telephone Laboratories, Inc.
A high-speed, self-checking count circuit realization is attainable by using combinational logic and parity prediction. The utilization of combinational logic as opposed to sequential logic design generally minimizes the amount of software necessary for routine and diagnostic testing. Count circuits with parity prediction find application in stand-alone, self-checking processors.
Binary counter, error detection, integrated circuits, parallel counter, parity generation, parity prediction, self-checking logic.

R. Dorr, "Self-Checking Combinational Logic Binary Counters," in IEEE Transactions on Computers, vol. 21, no. , pp. 1426-1430, 1972.
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