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Issue No. 12 - December (1972 vol. 21)
ISSN: 0018-9340
pp: 1421-1426
S.M. Reddy , Department of Electrical Engineering, University of Iowa
A technique to design fault-locatable combinational switching circuits is given. The networks resulting from the application of the proposed technique have at most three levels of gates.
Fault-locatable designs, fault location, stuck-at faults, unate functions.
S.M. Reddy, "A Design Procedure for Fault-Locatable Switching Circuits", IEEE Transactions on Computers, vol. 21, no. , pp. 1421-1426, December 1972, doi:10.1109/T-C.1972.223517
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