Issue No. 12 - December (1972 vol. 21)

ISSN: 0018-9340

pp: 1365-1373

J.R. Story , Department of Electrical Engineering, University of Miami

ABSTRACT

The problem of encoding the internal states of synchronous sequential switching circuits so as to minimize the combinational network cost is treated. Cost is defined as the number of AND-OR inputs required in the two-level implementation of each memory element input equation separately ( i.e., the cost is not reduced initially by the existence of common terms between equations). An algorithm has been developed that considers implicitly all distinct state-assignment schemes for a given state table, thus ensuring that the state assignment that results in the least "cost" combinational network is selected. Since any optimum state-assignment scheme is dependent on the type of memory element, the algorithm is designed for use with J-K flip-flop memory elements because of their wide use and versatility.

INDEX TERMS

General J-K input equation, minimum number, partial state assignment, sequential circuit design algorithm, stateassignment optimization.

CITATION

H.J. Harrison, J.R. Story, E.A. Reinhard, "Optimum State Assignment for Synchronous Sequential Circuits",

*IEEE Transactions on Computers*, vol. 21, no. , pp. 1365-1373, December 1972, doi:10.1109/T-C.1972.223508