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Issue No.12 - December (1972 vol.21)
pp: 1331-1336
D.K. Pradhan , Department of Electrical Engineering, University of Iowa
A new error-control technique for logic processors is given. The proposed technique uses Reed-Muller codes (RMC's). The design scheme given has better efficiency than the schemes proposed earlier. The improved efficiency is obtained by relaxing a basic assumption originally made by Elias. Furthermore, it is shown that the efficiency of the proposed scheme asymptotically approaches the maximum efficiency achievable by a practical though restricted class of error-control schemes. Reliability of the proposed scheme is studied.
Error control, expurgated codes, Hamming code decoder, logic processors, modulo-2 sum of products form, Reed-Muller codes.
D.K. Pradhan, S.M. Reddy, "Error-Control Techniques for Logic Processors", IEEE Transactions on Computers, vol.21, no. 12, pp. 1331-1336, December 1972, doi:10.1109/T-C.1972.223504
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