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Issue No. 06 - June (1972 vol. 21)
ISSN: 0018-9340
pp: 598-602
K. Vairavan , Department of Electrical Engineering, University of Wisconsin-Milwaukee, Milwaukee, Wis. 53201.
A finite-state machine (FSM) is said to have finite input-memory, ¿<inf>i</inf> (finite output-memory ¿<inf>o</inf>) if ¿<inf>i</inf>(¿<inf>o</inf>) is the least integer such that y<inf>k</inf> = f(X<inf>k</inf>, X<inf>k-1</inf>,..., X<inf>k-¿i</inf>), (y<inf>k</inf> = f(X<inf>k</inf>, y<inf>k-1</inf>,..., y<inf>k-¿o</inf>)). If no such integer ¿<inf>i</inf>(¿<inf>o</inf>) exists then by convention ¿<inf>i</inf> = ¿ (¿ = ¿). It is well known that for a nondegenerate binary-input binary-output FSM M, ¿<inf>i</inf> ¿ [log2 n] (¿o ¿ [log2 n]), where n is the number of non-equivalent states in M. In this note we show that the above bound cannot be improved upon by giving a procedure to construct, for any n ≫ 0, a binary-input binary-output FSM with n nonequivalent states and minimal input-memory ¿<inf>i</inf> = [log<inf>2</inf> n] (minimal output-memory ¿<inf>o</inf> = [ log2 n]). In the process of proving the tightness of the lower bound on ¿<inf>i</inf>(¿<inf>o</inf>), we enumerate the number of distinct minimal binary r-stage feed-forward (output feedback) shift registers.

K. Vairavan, "Minimal Input-Memory and Output-Memory Finite-State Machines," in IEEE Transactions on Computers, vol. 21, no. , pp. 598-602, 1972.
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