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Issue No. 05 - May (1972 vol. 21)
ISSN: 0018-9340
pp: 464-471
D.B. Armstrong , Bell Telephone Laboratories, Inc.
A deductive method of fault simulation is described, which "deduces" the faults defected by a test at the same time that it simulates explicitly only the good behavior of logic circuit. For large logic circuits (at least several thousand gates) it is expected to be faster than "parallel" fault simulators, but uses much more computer memory than do parallel simulators.
Deductive method, error symptoms, fault dictionary, fault simulation, logic circuits, simulation, trouble location.

D. Armstrong, "A Deductive Method for Simulating Faults in Logic Circuits," in IEEE Transactions on Computers, vol. 21, no. , pp. 464-471, 1972.
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