The Community for Technology Leaders
Green Image
Issue No. 03 - March (1972 vol. 21)
ISSN: 0018-9340
pp: 301-305
Hudai Dirilten , Department of Electrical Engineering, Texas Technological College, Lubbock, Tex. 79409.
ABSTRACT
In earlier papers no analysis characterizing faulty four-phase MOS logic arrays due to single load and sampling transistor faults has been given. In this note the models due to faulty load and sampling transistors are analyzed and discussed. Some useful results leading to faster simulation of four-phase MOS logic arrays with single faulty load and sampling transistors are presented. The computer simulation run time is reduced by one half for single-load transistor faults. At the end of each bit a shorted sampling transistor does not introduce any error for gate types 2 and 3 when initialization is with phase-4 time and for gate types 1 and 4 when initialization is with phase-2 time.
INDEX TERMS
CITATION
Hudai Dirilten, "On the Mathematical Models Characterizing Faulty Four-Phase MOS Logic Arrays", IEEE Transactions on Computers, vol. 21, no. , pp. 301-305, March 1972, doi:10.1109/TC.1972.5008954
98 ms
(Ver 3.3 (11022016))