Issue No. 12 - December (1971 vol. 20)
J.P. Hayes , IEEE
This paper considers the design of combinational logic circuits which require a minimal or near-minimal number of tests. Bounds on the number of tests required by various network structures are considered. It is shown that for an n-input fanout-free network, the number of single and multiple fault detection test lies between 2 vn and n + 1, while the number of fault locations tests lies between 2 vn and 2n.
Bounds on the number of tests, combinational networks, design of diagnosable networks, fault diagnosis, linear Boolean functions, minimum-test realizations.
J.P. Hayes, "On Realizations of Boolean Functions Requiring a Minimal or Near-Minimal Number of Tests", IEEE Transactions on Computers, vol. 20, no. , pp. 1506-1513, December 1971, doi:10.1109/T-C.1971.223163