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Issue No. 12 - December (1971 vol. 20)
ISSN: 0018-9340
pp: 1496-1506
J.P. Hayes , IEEE
A network model colled the normal NAND model is introduced for the study of fault diagnosis in combinational logic circuits. It is shown that every network can be transformed into an equivalent normal NAND network from which all the information pertaining to the diagnosis of the original network con be obtained. The use of this model greatly simplifies fault analysis and test generation.
Combinational networks, fault diagnosis, fault masking, indistinguishable faults, multiple fault detection, NAND networks.
J.P. Hayes, "A Nand Model ror Fault Diagnosis in Combinational Logic Networks", IEEE Transactions on Computers, vol. 20, no. , pp. 1496-1506, December 1971, doi:10.1109/T-C.1971.223162
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