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A straightforward efficient computer algorithm for synthesizing multiple-output NAND (NOR) switching networks is presented which takes practical fan-in and fan-out limitations of logic gates into account. The algorithm is highly iterative and hence is very suitable for realizing large-size switching functions by a digital computer. The algorithm has been programmed in Fortran and a great deal of statistical data has been obtained to demonstrate its efficiency in terms of gate count as well as computing time. It is also efficient for hand execution
Algorithm, combinational logic, design automation, factoring, fan-in limit; fan-out limit, minimization techniques, multiple-output, NAND ( NOR) synthesis, switching circuits, switching functions.
null Chong-Woo Nam, S.Y.H. Su, "Computer-Aided Synthesis or Multiple-Output Multilevel NAND Networks witk Fan-in and Fan-out Constraints", IEEE Transactions on Computers, vol. 20, no. , pp. 1445-1455, December 1971, doi:10.1109/T-C.1971.223156
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