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TABLE OF CONTENTS
Issue No. 11 - November (vol. 20)
ISSN: 0018-9340
Papers

Fault-Tolerant Computing: An Introduction and an Overview (Abstract)

C.V. Ramamoorthy , Departments of Electrical Engineering and Computer Sciences, University of Texas, Austin, Tex. 78712
pp. 1241-1244

An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits (Abstract)

S.S. Yau , Departments of Electrical Engineering and Computer Sciences and the Biomedical Engineering Center, Northwestern University, Evanston, 111. 60201
Yu-Shan Tang , Department of Electrical Engineering, Northwestern University, Evanston, 111. 60201
pp. 1245-1251

Cause-Effect Analysis for Multiple Fault Detection in Combinational Networks (Abstract)

D.C. Bossen , IBM Systems Development Division, Poughkeepsie, N. Y. 12602
Se June Hong , IBM Systems Development Division, Poughkeepsie, N. Y. 12602
pp. 1252-1257

Algorithms for Detection of Faults in Logic Circuits (Abstract)

W.G. Bouricius , IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.
E.P. Hsieh , IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.
G.R. Putzolu , IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.
J.P. Roth , IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.
P.R. Schneider , IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.
C. Tan , IBM Thomas J. Watson Research Center, Yorktown Heights, N. Y.
pp. 1258-1264

Derivation of Minimum Test Sets for Unate Logical Circuits (Abstract)

R. Betancourt , Instituto Tecnologico of Monterrey, Monterrey, Mexico.
pp. 1264-1269

Structural Factors in the Fault Diagnosis of Combinational Networks (Abstract)

J.D. Russell , Department of Electrical Engineering, University of Wisconsin, Madison, Wis.
C.R. Kime , Department of Electrical Engineering, University of Wisconsin, Madison, Wis.
pp. 1276-1285

Fault Equivalence in Combinational Logic Networks (Abstract)

E.J. McCluskey , Digital Systems Laboratory, Departments of Electrical Engineering and Computer Science, Stanford University, Stanford, Calif.
F.W. Clegg , Department of Electrical Engineering, University of Santa Clara, Santa Clara, Calif.
pp. 1286-1293

Computer Diagnosis Using the Blocking Gate Approach (Abstract)

C.V. Ramamoorthy , Department of Electrical Engineering, University of Texas at Austin, Austin, Tex. 78712
W. Mayeda , Department of Electrical Engineering and Coordinated Science Laboratory, University of Illinois, Urbana, Ill.
pp. 1294-1299

Logic Design for Dynamic and Interactive Recovery (Abstract)

W.C. Carter , IBM Corporation, Yorktown Heights, N. Y. 10598
D.C. Jessep , IBM Corporation, Yorktown Heights, N. Y. 10598
A.B. Wadia , IBM Corporation, Yorktown Heights, N. Y. 10598
P.R. Schneider , IBM Corporation, Yorktown Heights, N. Y. 10598
W.G. Bouricius , IBM Corporation, Yorktown Heights, N. Y. 10598
pp. 1300-1305

Reliability Modeling for Fault-Tolerant Computers (Abstract)

W.G. Bouricius , T. J. Watson Research Center, IBM Corporation, Yorktown Heights, N. Y. 10598
W.C. Carter , T. J. Watson Research Center, IBM Corporation, Yorktown Heights, N. Y. 10598
D.C. Jessep , T. J. Watson Research Center, IBM Corporation, Yorktown Heights, N. Y. 10598
P.R. Schneider , T. J. Watson Research Center, IBM Corporation, Yorktown Heights, N. Y. 10598
A.B. Wadia , T. J. Watson Research Center, IBM Corporation, Yorktown Heights, N. Y. 10598
pp. 1306-1311

The STAR (Self-Testing And Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer Design (Abstract)

A. Avizienis , Jet Propulsion Laboratory, California Institute of Technology, Pasadena, Calif. 91103, and the Department of Computer Science, University of California, Los Angeles, Calif. 90024
G.C. Gilley , Jet Propulsion Laboratory, California Institute of Technology, Pasadena, Calif. 91103, and the Department of Computer Science, University of California, Los Angeles, Calif. 90024
F.P. Mathur , Jet Propulsion Laboratory, California Institute of Technology, Pasadena, Calif. 91103
D.A. Rennels , Jet Propulsion Laboratory, California Institute of Technology, Pasadena, Calif. 91103
J.A. Rohr , Jet Propulsion Laboratory, California Institute of Technology, Pasadena, Calif. 91103
D.K. Rubin , Jet Propulsion Laboratory, California Institute of Technology, Pasadena, Calif. 91103
pp. 1312-1321
Papers

IEEE Computer Society (PDF)

pp. c2

Analysis of Parallel Systems (Abstract)

T.H. Bredt , IEEE
pp. 1403-1407

Contributors (PDF)

pp. 1415-1419

Blank Page (PDF)

pp. 1435

Information for Authors (PDF)

pp. 1435
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