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Issue No.08 - August (1971 vol.20)
pp: 882-888
This paper introduces two schemes to correct bit errors caused by defective memory cells in high-speed random-access memory systems. The schemes are addressed to word-organized memories produced by the integrated technologies. One of the two schemes calls for encoding of input information and the other does not. The schemes are simple, economical for the technologies concerned, and exhibit a regularity which makes it possible to fabricate the necessary additional hardware within the same technology.
Cell defects, coding, error correction, integrated, memories.
C.V. Srinivasan, "Codes for Error Correction in High-Speed Memory Systems?Part I: Correction of Cell Defects in Integrated Memories", IEEE Transactions on Computers, vol.20, no. 8, pp. 882-888, August 1971, doi:10.1109/T-C.1971.223365
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