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ABSTRACT
A circuit for generating a clock pulse for asynchronous circuits is given, and when used with transition sensitive flip-flops eliminates critical races for an arbitrary state assignment. Thus the minimum number of internal variables may be used. Furthermore, logic and sequential hazards will not affect the circuit performance.
INDEX TERMS
Asynchronous sequential circuits, critical races, hazards, transition sensitive flip-flops.
CITATION
J.G. Bredeson, P.T. Hulina, "Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races", IEEE Transactions on Computers, vol. 20, no. , pp. 225-226, February 1971, doi:10.1109/T-C.1971.223219
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